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| a PRELIMINARY TECHNICAL DATA Advanced Video Decoder with 9-Bit ADC, & Component Input Support Preliminary Technical Data ADV7183 YCrCb (4:2:2 or 4:1:1) CCIR601/CCIR656 8-Bit 0.5V to 2.0V pk-pk i/p range Differential Gain typ 1% Differential Phase typ 1o Programmable Video Controls Pk-White/Hue/Brightness/Saturation/Contrast CCIR/Square Pixel Operation Integrated On-Chip Video Timing Generator Synchronous or Asynchronous Output Timing Line Locked Clock Output Close Captioning Passthrough Operation Vertical Blanking Interval Support Power Down Mode 2-Wire Serial MPU Interface (I2C Compatible) +5V Analog +3.3V Digital CMOS Supply Operation 80-Pin LQFP Package APPLICATIONS DVD-RAM or DVD-R Digital TV's Video Conferencing Hybrid Analog/Digital Set Top Boxes PC Video/Multimedia Camcorders Security Systems/Surveillance FEATURES Analog Video to Digital YUV Video Decoder NTSC-(M/N), PAL-(B/D/G/H/I/M/N) Integrates Two 9-Bit Accurate ADCs Clocked from a Single 27 MHz Crystal Dual Video Clocking Schemes Line Locked Clock Compatible (LLC) Fixed Frequency Oversamping 10-Bit Operation Adaptive-Digital-Line-Length-Tracking (ADLLT) Real Time Clock & Status Information Output Integrated AGC (Automatic Gain Control) & Clamping Simplified Digital Interface On-Board Digital FIFO Optimised Programmable Video Source Modes Broadcast TV VCR/Camcorder Security/Surveillance Multiple, Programmable Analog Input Formats: CVBS (Composite Video) SVHS (Y/C) YPrPb ot YUV 6 Analog Input Video Channels 2 Line Chroma Comb Filter Automatic NTSC/PAL Identification VMI & VIP compliant video pixel port Digital Output Formats (16-Bit Wide Bus): GENERAL DESCRIPTION The ADV7183 is an integrated video decoder that automatically recognises and converts a standard analog baseband television signal compatible with world wide standards NTSC or PAL into 4:2:2 or 4:1:1 component video data compatible with 16-bit/8-Bit CCIR601/ CCIR656 8-Bit standards. The advanced and highly flexible digital output interface enables perfomance video decoding and conversion in both frame-buffer based and line locked clock based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics including tape based sources, broadcast sources, secruity/surveillance cameras and professional systems. Fully integrated line stores enable real time horizontal and vertical scaling of captured video down to icon size. The 9-bit accurate A/D conversion provides professional quality SNR performance. This allows true 8-bit resolution in the 8-bit output mode. The 6 analog inputs channel accept standard composite, S-Video and Component YPrPb video signals in an extensive number of combinations. AGC and Clamp Restore circuitry allow an input video signal peak to peak range of 0.5V up to 2V. Alternatively these can be bypassed for manual settings. The fixed 27 MHz clocking of the ADCs and datapath for all modes allows very precise and accurate sampling and digital filtering. The Line Locked Clock output allows the output data rate, timing signals and output clock signals to be synchronous, asynchronous or line locked even with +/-5% line length variation. The output control signals allow glueless interface connection in almost any application. The ADV7183 modes are set up over a two wire serial bidirectional port (I2C compatible). The ADV7183 is fabricated in a +5V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7183 is packaged in a small 80 pin LQFP package. * ADV is a Registered Trademark of Analog Devices, Inc. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 2001 Rev. PrF 09/01 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Rev. PrF 09/01 ADV7183 ISO A D V 7183 P15-P 0 PIXE L O /P PO RT PEAKING HPF /LPF & PIXEL O UTP UT F O R M AT T ER CHRO M A CHO M B F ILTE R F IF O C O N T RO L BLO CK AF F HFF/Q CLK AEF DV RD RESAM P LING & HO RIZ O NT AL SCALING LUM A AN T I-ALIAS LPF REFO UT AIN1 AN ALO G I/P M U LTIPLEXING 10 -B IT ADC SHAP ING & NO T CH LPF AIN2 AIN3 SUB-CARRIER RECO VERY DTO AU T O M AT IC G AIN CONTROL (AG C ) 27M Hz SYNC DET ECT IO N 2H LINE M EM O RY OE G L/C LKIN PRELIMINARY TECHNICAL DATA 2 SW ITCH CHRO MA ANT I-ALIAS LPF SHAPING LPF RESAM P LING & HO RIZ O NT AL SCALING LUM A DELA Y BLO CK VIDEO T IM ING & C O N TR O L BLO C K 27M H z XT AL O SC ILLA T O R BLO C K F IELD H RE F VR EF VSY N C AIN4 C LA M P & LLC1 LLC2 LLCREF AIN5 D C R EST O R E 10 -B IT ADC LLC SYNTHESIS W ITH LINE LO CK ED O UTPUT CLO CK AIN6 I 2 C C O M P AT IB LE INT ER F AC E PO R T ELP F PW RDN H SY N C CLO CK CLO CK RESE T SDATA SCLO CK ALSB FUNCTIONAL BLOCK DIAGRAM PRELIMINARY TECHNICAL DATA PIN DESCRIPTION ADV7183 Mnemonic P15-P0 GPO[0:3] XTAL XTAL1 DVSS1-3 DVDD1-3 DVDDIO DVSSIO AVSS AVDD AVSS1-6 AIN1-6 SCLOCK SDATA ALSB Input/Output Function O O I 0 G P P G G P G I I I/O I Vidoe pixel output port. 8-Bit Multiplexed YCrCb Pixel Port (P15-P8), 16-Bit YCrCb Pixel Port (P15-P8=Y & P7-P0=Cb,Cr). General purpose outputs controlled via I2C. Input terminal for 27MHz crystal oscillator or connection for external oscillator with CMOS compatible square wave clock signal Second terminal for crystal oscillator; not connected if external clock source is used Ground for Digital supply Digital Supply Voltage (+3.3V ) Digital I/O supply Voltage (+3.3V) Digital I/O ground Ground for Analog Supply Analog Supply Voltage (+5V) Analog Input Channels ground if single ended mode is selected. These pins should be nected directly to REFOUT in Differential mode is selected. Video Analog Input Channels MPU Port Serial Interface Clock Input. MPU Port Serial Data Input/Output. TTL Address Input, it selects the MPU address; MPU address = 88H ALSB = 0, diables I2C filter MPU address = 8AH ALSB = 1, enables I2C filter Asynchronous FIFO Read Enable signal. A logical high on this pin enables a read from the output of the FIFO. DV or Data Valid output signal. In SCAPI/CAPI mode: DV performs a two functions depending on whether SCAPI or CAPI is selected. It toggles high when the FIFO has reached the AFF margin set by the user, and remains high until the FIFo is empty. The alternative mode is where it can be used to control FIFO reads for bursting information out of the FIFO. In API mode DV indicates valid data in the FIFO, which includes both pixel information and control codes. The polarity of this pin is controlled via PDV. Output Enable controls pixel port outputs. A logical high will tri-state P19-P0. Dual function pin, HREF or Horizontal Reference output signal (enabled when Line Locked Interface is selected , OM_SEL[1:0] = 0,0); this signal is used to indicate data on the YUV output. The positive slope indicates the begining of a new active line, HREF is always 720 Y samples long. HRESET or Horizontal Reset Output (enabled when SCAPI or CAPI is selected, OM_SEL[1:0] = 0,1 or 1,0) is a signal the indicates the begining of a new line of video. In SCAPI/CAPI this signal is one clock cycle wide and is output relative to CLKIN. It immediately follows the last active pixel of a line. The polarity is controlled via PHVR. con RD DV I O OE HREF/HRESET I O 3 Rev. PrF 09/01 ADV7183 Mnemonic VREF/VRESET PRELIMINARY TECHNICAL DATA PIN DESCRIPTION Input/Output Function O VREF or Vertical Reference output signal, indicates start of next field). VRESET or Vertical Reset Output is a signal that indicates the begining of a new field. In SCAPI/ CAPI mode this signal is one clock wide and active low relative to CLKIN. It immedi ately follows HRESET pixel, and it indicates that the next active pixel is the first active pixel of the next field. Clock reference ouput; this is a clock qualifier distributed by the internal CGC for a data rate of LLC2. The polarity of LLCREF is controlled by PLLCREF bit. Dual function pin, Line Locked Clock system output clock (27MHz 5%) or a FIFO output clock ranging from 20-35MHZ. Line locked clock system output clock/2 (13.5MHz). This pin is used for the External Loop Filter that is required for the LLC PLL. System Reset, can be configured as an Input or Output signal (the RES bit can be used to control this pin). Power Down enable, a logical low will place part in a power down status. Internal Voltage Reference Output. Common Mode Level for ADC. Almost Empty Flag is a FIFO control signal. It indicates when the FIFO has reached the almost empty margin set by the user (use FFM[4:0]). The ploarity of this signal is controled by PFF bit. Multi function pin, Half Full Flag (OM_SEL[1:0] = 1,0) is a FIFO control signal which indicates when the FIFO is half full. The QCLK (OM_SEL[1:0] = 0,1) pin function is a qualified pixel output clcok when using FIFO SCAPI mode. The GL (OM_SEL[1:0] = 0,0) function (Genlock output) is a signal that contains a serial stream of data which contains information for locking the subcarrier frequency. The ploarity of HFF signal is controled by PFF bit. Almost Full Flag is a FIFO control signal. It indicates when the FIFO has reached the almost full margin set by the user (use FFM[4:0]). The ploarity of this signal is controled by PFF bit. CLKIN is an asynchronous FIFO clock. This asynchronous clock is used to output data onto the P19-P0 bus and other control signals. The LLC1 clock can be tied to this pin and the frequency programmed by CLKVAL[17:0]. ODD/EVEN field output signal. A active state indicates that an even field is being digitized. The polarity of this signal is controlled by PF bit. Dual function pin, HS or Horizontal Sync (OM_SEL[1:0] = 0,0) is a programmable horizontal sync output signal. The rising and falling edges can be controlled by HSB[9:0] and HSE[9:0] in steps of 2 LLC1. The ploarity of HS signal is controled by PHS bit. HACTIVE (OM_SEL[1:0] = 1,0 or 0,1) is an output signal that is active during the active/viewable period of a video line. The active portion of a video line is programmable on the ADV7183. polarity of HACTIVE is controlled by PHS bit. Dual function pin, VS or Vertical Sync (OM_SEL[1:0] = 0,0) is an output signal that indicates a vertical sync with respect to the YUV pixel data. The active period of this signal is six lines of video long. The ploarity of VS signal is controled by PVS bit. VACTIVE (OM_SEL[1:0] = 1,0 or 0,1) is an output signal that is active during the active/viewable period of a video field. The polarity of VACTIVE is controlled by PVS bit. 4 LLCREF LLC1/PCLK LLC2 ELPF RESET PWRDN REFOUT CML AEF O O O I I/O I O O O HFF/QCLK/GL I/O AFF CLKIN O I FIELD HS/HACTIVE O O The VS/VACTIVE O Rev. PrF 09/01 PRELIMINARY TECHNICAL DATA PIN DESCRIPTION ADV7183 Mnemonic Input/Output Function ISO I ISO (Input Switch Over) a low to high transition on this input indicates to the decoder core that the input video source has been changed externally and configures the deocder to reacquire the new timing infromation of the new source. This is useful in applica tions where external video muxs are used. This input gives the advantage of faster locking to the external muxed video sources. A low to high transisition trigers this input. ADC Capacitor network. ADC Capacitor network. CAPY1-2 CAPC1-2 I I 5 Rev. PrF 09/01 ADV7183 PRELIMINARY TECHNICAL DATA * VAA to GND.............................................................7V Voltage on any Digital Input Pin...........GND-0.5V to VAA+0.5V Storage Temperature (TS)....................-65OC to +150OC Junction Temperature(TJ)..................................+150OC Lead Temperature (Soldering, 10 secs)................+260C Analog Outputs to GND1.....................GND -0.5 to VAA NOTES * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration. ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Model Option Temperature Range Package ADV7183KST 0oC to 70oC 80 LQFP 7 0 HR EF/H R E S E T 6 9 VR EF/V R E S E T 7 2 DV D D3 7 1 DV S S 3 64 RESET 6 7 SD AT A 8 0 FIELD 6 6 A LS B 6 3 AVS S 6 8 SC LK VS /VAC T VE HS/HACT IV E DV SSIO DVD DIO P11 P10 P9 P8 DV S S 2 AFF AE F DV SSIO DVD DIO 1 2 3 4 5 6 7 8 9 11 13 14 15 PIN 1 IDEN T IF IER 78 DV 6 2 AIN6 7 4 P 14 7 5 P 13 6 5 IS O 7 7 RD 6 1 AVS S 6 60 AIN5 59 AV S S 5 58 AIN4 57 AV S S 4 56 AV S S 55 CA P C 2 54 CA P C 1 53 AV S S 52 C M L 51 RE FO UT 50 AV D D 49 CA P Y2 48 CA P Y1 47 AV S S 46 AIN3 45 AV S S 3 44 AIN2 43 AV S S 2 42 AIN1 41 AV S S 1 7 6 P 12 DV D D2 10 H F F/Q C LK/G L 12 CLKIN 16 G P O 3 17 G P O 2 18 P 7 19 P 6 20 7 3 P 15 79 O E AD V 71 83 T O P VIEW (Not to Sc ale) LLC 2 26 LLC 1/P CLK 27 P 2 24 LL C R EF 25 P W R D N 36 DV D D1 30 DV S S 1 31 XT A L1 28 XT AL 29 G P O 1 34 G P O 0 35 PVD D 38 ELP F 37 P 5 21 P 4 22 P 3 23 P 1 32 P 0 33 PVS S 39 ADV7183 PIN FUNCTIONALITY Rev. PrF 09/01 6 AVS S 40 PRELIMINARY TECHNICAL DATA ADV7183 SPECIFICATIONS1 Parameter STATIC PERFORMANCE Resolution (each ADC) Accuracy (each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL High Impedance Leakage Current Output Capacitance VOLTAGE REFERENCE Reference Range, VREFOUT POWER REQUIREMENTS Digital Power Supply, VDD Analog Power Supply, VAA Digital Supply Current, I DD3 Digital Supply Current, I DD3 Analog Supply Current, IAA4 Analog Supply Current, IAA4 Power-up Time (VAA = + 5V 5%, VDD = + 3.3V 5%, VDDIO=+3.3V 5% All specifications TMIN to TMAX 2 unless otherwise noted) Min Typ Max 9 0.5 0.5 Units Bits LSB LSB Guaranteed Monotonic Test Conditions 2 -10 0.8 10 10 V V A pF V V A pF V VIN = 0.4V or 2.4V 2.4 0.4 10 30 2.1 ISOURCE = 3.2 mA ISINK = 0.4 mA IVREFOUT = 0A 3.15 4.75 3.3 5.0 150 154 150 150 1 3.45 5.25 V V mA mA mA mA field CVBS, CCIR-656, V DD=3.3V CBVS, PAL Sq Pixel,VDD=3.3V CVBS, CCIR-656,V AA= 5.25V CVBS, PAL Sq Pixel,VAA= 5.25V Sleep mode until powered up NOTE 1 The max/min specifications are guaranteed over this range. The max/min values are typical over VAA = 4.75V to 5.25V 3.15V to 3.45V range 2 Temperature Range TMIN to TMAX: 0oC to 70oC. 3 IDD is total current taken by DVDD & DVDIO supply pins. 4 I AA is total analog current taken by AVDD supply pins. and VDD/VDDIO = Specifications subject to change without notice. 7 Rev. PrF 09/01 ADV7183 Parameter PRELIMINARY TECHNICAL DATA (VAA = + 5V 5%, VDD = +3.3 5%, VDDIO=+5V/3.3 5% All specifications TMIN to TMAX 2 unless otherwise noted) Test Conditions CVBS, Comb/No Comb CVBS, Comb/No Comb VIDEO PERFORMANCE SPECIFICATIONS1 Min Typ 1 1 1 1 60 57 63 63 Max NON-LINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Non-Linearity Chroma Non-Linear Gain NOISE SPECIFICATIONS SNR (Pedestal) SNR (Ramp) Analog Front End Channel Crosstalk Analog Front End Channel Crosstalk LOCK TIME AND JITTER SPECIFICATIONS Horizontal Lock Time Horizontal Recovery Time Horizontal Lock Range Line Length Variation Over Field Line Length Variation Over Field HLock Lost Declared HLock Lost Declared Vertical Lock Time VLock Lost Declared FSC Subcarrier Lock Range Color Lock Time LLC Clock Jitter (Short Time Jitter) LLC Clock Jitter (Frame Jitter) CHROMA SPECIFIC SPECIFICATIONS Hue Accuracy Color Saturation Accuracy Color Gain Control Range Analog Color Gain Range Digital Color Gain Range LUMA SPECIFIC SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy deg % % % dB dB dB dB Units CVBS CVBS S-Video/ YUV, single ended S-Video/ YUV, differential ended 10 50 50 5 1 1 20 2 1 400 50 1 37 1 1 -6 -6 0 1.0 1.0 lines lines % % % HSync HSync VSync VSync Hz lines ns ns deg % dB dB dB % % TV / VCR mode VCR mode/ Surveillance mode TV mode TV mode, No. of missing HSyncs VCR/Surveillance mode, No. of missing HSyncs First Lock into video signal All modes, No. of missing VSyncs NTSC/PAL HLock to Color Lock Time RMS Clock Jitter RMS Clock Jitter 18 6 12 S-Video, YUV, Overall CGC Range(analog and digital) S-Video, YUV CVBS, S-Video, YUV Video Input Range Video Input Range = 1.0Vp-p = 1.0Vp-p NOTE 1 The max/min specifications are guaranteed over this range. 3.15V to 3.45V range 2 Temperature Range TMIN to TMAX: 0oC to 70oC. The max/min values are typical over VAA = 4.75V to 5.25V and VDD/VDDIO = Specifications subject to change without notice. Rev. PrF 09/01 8 PRELIMINARY TECHNICAL DATA ADV7183 TIMING SPECIFICATIONS1 Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency I C PORT SCL Clock Frequency SCL min pulse width high, t1 SCL min pulse width low, t2 Hold Time (Start Condition), t3 Setup time (Start Condition), t4 Data Setup Time, t5 SCL/SDA Rise Time, t6 SCL/SDA Fall Time, t7 Setup Time (Stop Condition), t8 RESET FEATURE Reset Pulse Input Width CLOCK OUTPUTS LLC1 Cycle Time, t9 LLC1 Cycle Time, t9 LLC1 Cycle Time, t9 LLC1 min low period, t10 LLC1 min high period, t11 LLC1 falling to LLCREF falling, t12 LLC1 falling to LLCREF rising, t13 LLC1 rising to LLC2 rising, t14 LLC1 rising to LLC2 falling, t15 CLKIN Cycle Time, t18 DATA AND CONTROL OUTPUT Data Output Hold Time, t17 Data Output Access Time, t16 Data Output Access Time, t19 Data Output Hold Time, t20 Propagation Delay to HiZ, t21 Max Output Enable access Time , t22 Min Output Enable access Time , t23 2 (VAA = + 5V 5%, VDD = /3.3V 5%, VDDIO = +3.3V 5% All specifications TMIN to TMAX 2 unless otherwise noted) Typ 27 Max Units MHz 400 kHz s s s s ns ns ns s s 37 33.9 40.8 18 18 4 6 3 2 37 8 28 20 10 5 8 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CCIR601 mode 27MHz PAL Square Pixel mode 29.5MHz NTSC Square Pixel mode 24.5MHz CCIR601 mode 27MHz CCIR601 mode 27MHz Test Conditions Min 0 0.6 1.3 0.6 0.6 100 0.6 tbd 300 300 SCAPI & CAPI modes LLC mode LLC mode SCAPI & CAPI modes SCAPI & CAPI modes NOTE 1 The max/min specifications are guaranteed over this range. 3.15V to 3.45V range 2 Temperature Range TMIN to TMAX: 0oC to 70 oC. The max/min values are typical over VAA = 4.75V to 5.25V and VDD/VDDIO = Specifications subject to change without notice. 9 Rev. PrF 09/01 ADV7183 Parameter CLAMP CIRCUITRY External Clamp Capacitor Input Impedance Voltage Clamp Level Clamp Source Current Clamp Sink Current Clamp Source Current Clamp Sink Current PRELIMINARY TECHNICAL DATA (VAA = + 5V 5%, VDD = +3.3 5%, VDD = + 5V/3.3 5%, 2 MIN to TMAX unless otherwise noted) Units F k V A A mA mA Test Conditions ANALOG FRONT END SPECIFICATIONS1 All specifications T Min Typ 0.1 500 1.4 +4 -4 +0.9 -0.8 Max Clamp switched off Signal already clamped (fine clamping) Signal already clamped (fine clamping) Aquire mode (fast clamping) Aquire mode (fast clamping) NOTE 1 The max/min specifications are guaranteed over this range. 3.15V to 3.45V range 2 Temperature Range TMIN to TMAX: 0oC to 70oC. The max/min values are typical over VAA = 4.75V to 5.25V and VDD/VDDIO = Specifications subject to change without notice. Rev. PrF 09/01 10 PRELIMINARY TECHNICAL DATA ADV7183 t5 t3 SDATA t3 t6 t1 S C LO C K t2 t7 t4 t8 Figure 2. MPU Port Timing Diagram Figure 3. LLC Clock, Pixel Port & Control Outputs Timing Diagram 11 Rev. PrF 09/01 ADV7183 C L KIN PRELIMINARY TECHNICAL DATA t 18 t 19 t 20 O U T PU T S P0 - P1 5, H R E F , VR EF , VS Y N C ,H SY N C , F IE L D , AF F ,AE F ,H FF Figure 4. Pixel Port & Control Outputs in CAPI & SCAPI mode Timing Diagram OE t22 PO-P15, H S, VS, H REF , VREF, FIE LD DV & G PO [3:0] t23 t21 Figure 5 OE Timing Diagram Rev. PrF 09/01 12 PRELIMINARY TECHNICAL DATA FUNCTIONAL DESCRIPTION ADV7183 ANALOG INPUT PROCESSING The ADV7183 has 6 analog video input channels. These 6 channels can be arranged in a variety of configurations to support up to 6 CVBS input signals, 3 S-Video inputs signals and 2 YCrCb component analog video inputs signals. The INSEL[3:0] control the input type and channel selected . The analog front-end includes 3 clamp circuits for DC restore. There are 3 Sample and Hold Amplifiers prior to the ADC which are used to enable simultaneous sampling of up to 3 channels in a YCrCb input mode. There are 2 9-bit ADC's used for sampling. The entire analog front-end is fully differential which ensures that the video is captured to the highest quality possible, this is very important in highly integrated systems like a video decoder. The block diagram below shows the analog front-end section on the ADV7183. 9 Figure XX. Analog Front-end Block Diagram CLAMPING The Clamp control on the ADV7183 consists of a digitally controlled analog current and voltage clamp and a digitally controlled digital clamp circuit. The coupling capacitor on each channel is used to store and filter the clamping voltage. A digital controller controls the Clamp up and down current sources which charge the capacitor on every line. There are four current sources used in the current clamp control, 2 large current sources are used for Course Clamping and two small current sources are used for Fine Clamping. The Voltage Clamp if enabled is only used on startup or if a channel is switched, this clamp pulls the video into the mid range of the ADC, this result in faster clamping and faster lock in time for the decoder. The fourth clamp controller is fully digital and clamps the ADC output data, this results in extremely accurate clamping, it also has the added advantage of being fully digital which result in very fast clamp timing and makes the entire clamping process very robust in terms of handling large amount of Hum which can be present on real world video signals. In S-Video mode there are 2 clamp controllers used to control the Luminance clamping and the Chrominance clamping separately. Also in YCrCb component input mode there are 2 clamp controllers used to control the Luminance clamping and the CrCb clamping separately, there is however individual current clamps on the Cr & Cb inputs. User programmability is built into the clamp controllers which enable the Current and Digital clamp controllers to be setup to user defined conditions. Refer to Analog Clamp Control Register(14H), Digital Clamp Control Register(15H) & Digital Color Clamp offset Register(15H & 16H) for control settings. 13 Rev. PrF 09/01 ADV7183 PRELIMINARY TECHNICAL DATA ANALOG TO DIGITAL CONVERTERS There are two 10-bit ADC used in the ADV7183. These ADC run off a 27MHz input clock. An integrate bandgap generates the required reference voltages for the converters. If the deocder in configured in CVBS mode the 2nd ADC can be switched off to reduce power consumption, see PSC[1:0]. AUTOMATIC GAIN CONTROL The AGC control block on the ADV7183 is a digitally based systems. This controller ensures that the input video signal (CVBS, S-Video or YCrCb) is scaled to its correct value such that the YCrCb digital output data matches the correct gain of the video signal. The AGC has an analog input video range of 0.5Vp-p to 2.0Vp-p which gives a -6dB to +6dB gain range, Figure xx below demonstrates this range. This AGC range will compensate for video signals that have been incorrectly terminated or have been attenuated due to cable loss etc. There are 2 main control blocks one for the Luminance channel and one for the Chrominance channel. The Luminance Automatic Gain Control has 8 modes of operation: 1)Manaual AGC mode where gain for luminance path is set manually using LGM[11:0]. 2)Blank Level to Sync tip used to set luminance gain, manual MIRE[2:0] controls max the value through Luminance channel. There is no override of this mode when White Peak mode is detected. 3)Blank Level to Sync tip used to set luminance gain, manual MIRE[2:0] controls max the value through Luminance channel. There is override of this mode when White Peak mode is detected. White peak mode is activated when the input video exceeds the max luminance range for long periods, this mode is designed to prevent clipping of the input video signal. 4)Blank Level to Sync tip used to set luminance gain, MIRE[2:0] is automatically controlled to set the max the value through luminance channel. There is no override of this mode when White Peak mode is detected. 5)Blank Level to Sync tip used to set luminance gain, manual MIRE[2:0] is automatically controlled to set the max the value through luminance channel. There is override of this mode when White Peak mode is detected. White peak mode is activated when the input video exceeds the max luminance range for long periods, this mode is designed to prevent clipping of the input video signal. 6)The Active video 7)The 8)The luminance channel gain is Frozen at it present value. an alo g in pu t leve l contr olled A D C inp ut lev el m a xim um 6 dB 0 dB 2 V (p- p) rang e 1 2 d B 0 dB -6 dB m inim u m M H B 325 Rev. PrF 09/01 14 PRELIMINARY TECHNICAL DATA The Chrominance Automatic Gain Control has 4 modes of operation: 1)Manaual AGC mode where gain for chrominance path is set manually using CGM[11:0]. 2)Luminance gain used for chrominance channel. 3)Chrominance automatic gain based on color burst amplitude. 4)Chrominance gain frozen at it present setting. ADV7183 Both the luminance and chrominance AGC controllers have programmable time constant which allows the AGC to operate in 4 modes, Slow,Medium, Fast & Video quality controlled. The max IRE (MIRE [2:0]) control can be used to set the max input video range that can be decoded. Figure xx shows the selectable range. M IR E [2 : 0 ] Fun ction PAL (IRE) 000 001 010 011 100 101 110 111 133 125 120 115 110 105 100 100 NTSC (IRE) 122 115 110 105 100 100 100 100 Figure XX. MIRE control 15 Rev. PrF 09/01 ADV7183 PRELIMINARY TECHNICAL DATA LUMINANCE PROCESSING Figure xx shows the luminance datapath. The 10-bit data from the Y ADC is applied to an Anti Aliasing Low Pass filter which is designed to bandlimt the input video signal such that alaising does not occur. This filter dramatically reduces the design on an external analog anti-alaising filter, this filter need only remove components in the input video signal above 22Mhz. The data then passes through a Shaping or Notch filter. When in CVBS mode a Notch filter must be used to remove the unwanted chrominance data the lays around the subcarrier frequency. A wide variety of programmable Notch filters for both PAL & NTSC are available. The YSFM[4:0] control the selection of these filters, refer to figure xx to figure xx for a plots of these filters. If S-Video or Component mode is selected a Notch filter is no required, the ADV7183 offers 18 possible shaping filters(SVHS1-18) with as range of low pass filter responses from 0.5Mhz up to 5.75MHz, YSFM[4:0] control the selection of these filters please refer to figure xx to figure xx for filter plots. The next stage in the luminance processing path is a Peaking filter, this filter offers a sharpness function on the Luminance path. The degree of sharpness can be selected using YPM[2:0]. If no sharpness is required this filter can be by-passed. The luminance data is then passed through a resampler to correct for line length variations in the input video. This resampler is designed to always output 720 pixels per line for standard PAL or NTSC. The resampler used on the ADV7183 is of very high quality as it uses 128 phases to resample the video, giving 1/128 pixel resolution. The resampler is controlled by a sync detection block which calculates line length variations on the input video. The final stage in the luminance path before it is applied to an output formatter block is a 2 line delay store which is used to compensate for dealys in the Chroma data path when Chroma Comb filter is selected. ADC DATA A ntiA lia sin g LP F S ha ping & No tc h Filter P ea king Filter Y Re sa m p le De la y Lin e S to res S ync Det ec tio n Figure XX. Luminance processing path Rev. PrF 09/01 16 PRELIMINARY TECHNICAL DATA LUMINANCE 0 SHAPING FILTER PLOTS ADV7183 S h aping F ilte r LP -R e spo nse s SVH S 1 SV H S 2 SV H S 16 SVH S 17 SV H S 4 SVH S 5 SVH S 6 SV H S 18 -10 SVH S3 -20 SV H S 7 SVH S8 A ttenu atio n (dB ) SVH S 9 SVH S 10 -30 SVH S1 1 SV H S 12 SVH S 13 SVH S 14 -40 SV H S 15 -50 -60 0 1 2 3 4 F req uen cy (M H z) 5 6 7 8 Figure xx. Luminance SVHS1-18 shaping filter responses S haping Filter LP -R esponses 1 0.8 0.6 0.4 0.2 A ttenuation (dB ) 0 -0.2 -0.4 -0.6 -0.8 -1 0 1 2 3 Frequency (M H z) 4 5 6 Figure xx. Luminance SVHS1-18 shaping filter responses (closeup) 17 Rev. PrF 09/01 ADV7183 0 PRELIMINARY TECHNICAL DATA S h ap in g F ilter N TS C no tche s -1 0 N TS C W N1 N TS C W N2 N TS C W N3 N TS C W N2 N TS C N N 3 N TS C W N1 N TS C N N 2 N TS C N N 1 N TS C W N3 -2 0 N TS C N N 1 N TS C N N 2 N TS C N N 3 A tten ua tion (dB ) -3 0 -4 0 -5 0 -6 0 0 1 2 3 4 F req ue ncy (M H z) 5 6 7 8 Figure xx. Luminance NTSC Narrow/Wide Notch shaping filter responses S h ap ing F ilte r N TS C n o tch es 1 0 .8 0 .6 0 .4 0 .2 A tten u a tio n (d B ) 0 -0 .2 N T SC W N 1 -0 .4 N T SC W N 2 N T SC W N 3 -0 .6 NTSC NN1 NTSC NN2 -0 .8 NTS C NN3 -1 0 0 .5 1 1 .5 2 Fre q ue n cy (M Hz) 2 .5 3 3 .5 4 Figure xx. Luminance NTSC Narrow/Wide Notch shaping filter responses (closeup) Rev. PrF 09/01 18 PRELIMINARY TECHNICAL DATA S ha ping Filter P A L Notches 0 ADV7183 PA L N N 2 PA L N N 3 PA L W 1 PA L W 2 PA L N N 1 PA L N N 1 -10 PA L N N 2 PA L N N 3 PA L W 1 -20 PA L W 2 A tte nuation (dB ) -30 -40 -50 -60 0 1 2 3 4 Frequency (M Hz) 5 6 7 8 Figure xx. Luminance PAL Narrow/wide Notch shaping filter responses Sha ping Filte r PAL No tches 1 0.8 0.6 0.4 0.2 Atte nua tio n (dB) 0 PAL NN1 -0 .2 PAL NN2 PAL W N1 PAL NN3 -0 .4 PAL W N2 -0 .6 -0 .8 -1 0 0.5 1 1.5 2 Freq uen cy (M H z) 2.5 3 3.5 4 Figure xx. Luminance PAL Narrow?Wide Notch shaping filter responses (closeup) 19 Rev. PrF 09/01 ADV7183 10 PRELIMINARY TECHNICAL DATA LUMINANCE PEAKING FILTER PLOTS 8 PS1 6 PS2 4 PS3 2 A tte n u ation (d B ) 0 PS4 PS5 -2 PS6 -4 -6 -8 0 1 2 3 4 Fre qu e n cy (M H z) 5 6 Figure xx. Luminance Peaking filter responses in S-Video (SVHS17 selected) 6 4 PC1 2 A tte nuation (dB ) PC2 0 PC3 PC4 PC5 -2 PC6 -4 -6 -8 10 0 1 2 3 F reque ncy (M H z) 4 5 6 Figure xx. Luminance Peaking filter responses in CVBS (PAL NN3 selected) Rev. PrF 09/01 20 PRELIMINARY TECHNICAL DATA 6 ADV7183 4 P C1 2 P C2 A ttenuation (dB ) 0 P C3 P C4 P C5 -2 P C6 -4 -6 Figure xx. Luminance Peaking filter responses in CVBS (NTSC NN3 selected) 21 Rev. PrF 09/01 ADV7183 PRELIMINARY TECHNICAL DATA CHROMINANCE PROCESSING Figure xx shows the chrominance datapath. The 10-bit data from the Y ADC (CVBS mode) or the C ADC (Svideo) is first demodulated. The demodulation is achieved by multiplying by the locally generated quadrature subcarrier, where the sign of the cos subcarrier is inverted from line to line according to the PAL switch, and then lowpass filtering is applied to removed components at twice the subcarrier frequency. For NTSC, the phase of the locally generated subcarrier during colour burst is the same as the phase of the colour burst. For PAL, the phase of the colour burst changes from line to line, relative to the phase during active video, and the phase of the locally generated subcarrier is the average of these two values. The chrominance data is then passed through a anti aliasing filter which is a bandpass filter to removed the unwanted luminance data. This anti alaising filter dramatically reduces the external anti alaising filter requirements as it has only to filter components above 25Mhz. In component mode the demodulation block is by-passed. The next stage of processing is a Shaping filter which can be used to limit the chrominance bandwidth too between 0.5Mhz and 3Mhz, the CSFM[2:0] can be used to select these responses. It should be noted that in CVBS mode a filter or no greater than 1.5Mhz should be selected as CVBS video is typically bandlimited to below 1.5Mhz. In SVideo mode a filter of up to 2Mhz can be used. In Component mode a filter of up to 3 Mhz can be used as component video has higher bandwidth than CVBS or S-Video. The chrominance data is then passed through a resampler to correct for line length variations in the input video. This resampler is designed to always output 720 pixels per line for standard PAL or NTSC. The resampler used on the ADV7183 is of very high quality as it uses 128 phases to resample the video, giving 1/128 pixel resolution. The resampler is controlled by a sync detection block which calculates line length variations on the input video. The final stage in the chrominance path before it is applied to an output formatter block is Chroma Comb filter. S in A nti- S y nc Detec tio n 13 .5 M H z X A lia sing LP F 27 M H z Interleav e C V /C C os A nti- S h ap ing LP F 6.75 M H z Re sa m p le U /V Ch ro m a Co m b Filters X A lia sing LP F 13 .5 M H z S ub ca rrie r Rec ov ery Figure XX. Chrominance processing path Rev. PrF 09/01 22 PRELIMINARY TECHNICAL DATA CHROMINANCE SHAPING FILTER L PLOTS C S haping Filter 0 ADV7183 SH1 -10 SH2 SH3 SH4 SH5 -20 SH6 A ttenuation (dB ) -30 -40 -50 -60 0 0.5 1 1.5 2 Frequency (M H z) 2.5 3 3.5 4 Figure xx. Chrominance shaping filter responses C S haping Filter 1 0.8 0.6 0.4 0.2 A ttenuation (dB ) 0 -0.2 SH1 -0.4 SH2 SH3 SH4 SH5 -0.6 SH6 -0.8 -1 0 0.5 1 1.5 2 Frequency (M H z) 2.5 3 3.5 4 Figure xx. Chrominance shaping filter responses (closeup) 23 Rev. PrF 09/01 ADV7183 PRELIMINARY TECHNICAL DATA NTSC OUTPUT TIMING DIAGRAMS C V B S In p u t HREF DV VREF VS Y N C FIE L D SA V /E A V V b it SA V /E A V H b it SA V /E A V F b it N TS C E nd E ven Field (L LC M O D E ) C V B S Inp ut HREF DV VREF VSY NC FIE LD S A V /E A V V b it S A V /E A V H bit S A V /E A V F bit N TS C E n d O d d Field (LLC M O D E ) Rev. PrF 09/01 24 PRELIMINARY TECHNICAL DATA PAL OUTPUT TIMING DIAGRAMS ADV7183 C V B S Inp ut HRE F DV VRE F V SY N C FIE LD S AV /EA V V b it S AV /EA V H bit S AV /EA V F bit P al E n d E ven Field (L LC M O DE ) C V B S Input HRE F DV VREF V SY N C FIE LD S AV /EA V V b it S AV /EA V H bit S AV /EA V F bit P A L E nd O d d Field (LLC M O DE ) 25 Rev. PrF 09/01 ADV7183 PRELIMINARY TECHNICAL DATA MPU PORT DESCRIPTION. The ADV7183 support a two wire serial (I2C Compatible) microprocessor bus driving multiple peripherals. Two inputs Serial Data (SDATA) and Serial Clock (SCLOCK) carry information between any device connected to the bus. Each slave device is recognised by a unique address. The ADV7183 has two possible slave addresses for both read and write operations. These are unique addresses for the device and are illustrated in Figure xx. The LSB sets either a read or write operation. Logic level "1" corresponds to a read operation while logic level "0" corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7183 to logic level "0" or logic level "1". 1 0 0 0 1 0 A1 X to the peripheral. A logic "1" on the LSB of the first byte means that the master will read information from the peripheral. The ADV7183 acts as a standard slave device on the bus. The data on the SDATA pin is 8 bits long supporting the 7-Bit addresses plus the R/W bit. The ADV7183 has 71 subaddresses to enable access to the internal registers. It therefore interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto increment allowing data to be written to or read from from the starting subaddress. A data transfer is always terminated by a Stop condition. The user can also access any unique subaddress register on a one by one basis without having to update all the registers. Stop and Start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, then these cause an immediate jump to the idle condition. During a given SCLOCK high period the user should only issue one Start condition, one Stop condition or a single Stop condition followed by a single Start condition. If an invalid subaddress is issued by the user, the ADV7183 will not issue an acknowledge and will return to the idle condition. If in auto-increment mode, the user exceeds the highest subaddress then the following action will be taken: 1. In Read Mode the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A noacknowledge condition is where the SDATA line is not pulled low on the ninth pulse. 2. In Write Mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7183 and the part will return to the idle condition. SD AT A AD D R ESS CONTROL SET U P BY ALS B R EAD / W R IT E CONTROL 0 1 W R IT E R EAD Fig xx. ADV7183 Slave Address To control the device on the bus the following protocol must be followed. First the master initiates a data transfer by establishing a Start condition, defined by a high to low transistion on SDATA whilst SCLOCK remains high. This indicates that an address/data stream will follow. All peripherals respond to the Start condition and shift the next eight bits (7-Bit address + R/W bit). The bits tranferred from MSB down to LSB. The peripheral that recognises the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDATA and SCLOCK lines waiting for the Start condition and the correct transmitted address. The R/W bit determines the direction of the data. A logic "0" on the LSB of the first byte means that the master will write information SC LO C K S 1-7 8 9 1-7 8 9 1-7 D AT A 8 9 AC K P ST O P ST AR T AD D R R / W AC K SU BAD D R ESS AC K Figure yy. Bus Data Transfer W R IT E SEQ U EN C E S SL AVE AD D R A(S ) L SB = 0 SU B A D D R A(S ) D AT A A(S ) L SB = 1 D AT A A(S ) P R EAD SEQ U EN C E S SL AVE AD D R S = ST A RT BIT P = ST O P B IT A(S ) SU B A D D R A(S ) S SL AVE AD D R A(S ) D AT A A(M ) D AT A A(M ) P A(S ) = AC KN O W L ED G E B Y S LA VE A(M ) = AC KN O W L ED G E BY M AST ER A (S) = N O -AC KN O W L E D G E BY SL AVE A (M ) = NO -AC KN O W L ED G E B Y M AST ER Figure 35 Illustrates an example of data transfer for a read sequence and the Start and Stop conditions. Rev. PrF 09/01 Figure 36. Write and Read Sequences 26 PRELIMINARY TECHNICAL DATA ADV7183 REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7183 except the Subaddress Register which is a write only register. The Subaddress Register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the Subaddress Register. Then a read/ write operation is performed from/to the target address which then increments to the next address until a Stop command on the bus is performed. REGISTER PROGRAMMING configuration. Subaddress Register (SR7-SR0) The Communications Register is an eight bit write-only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The Subaddress Register determines to/from which register the operation takes place. Figure 37 shows the various operations under the control of the Subaddress Register. Zero should always be written to SR7-SR6. Register Select (SR5-SR0): These bits are set up to point to the required starting address. Register N am e A D V A N C E D B LO C K The following section describes each register in terms of its Register N am e B A S IC B LO C K Inp ut C ontrol V ideo S election V ideo E nhanc ement C ontro l O utp ut C ontro l E xte nded O ut p ut C on trol G ene ral P urp ose O utp ut Reserved FIF O C o ntrol C ontras t C ontr ol S atu rati on C ontrol B right nes s C ontrol Hue C o ntrol D efault V alue Y D efault V alue C T em p ora l D eci m ation P ower M an agem ent S tatus Regis ter Info Regis ter addr (H ex) addr (H ex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 R e se rved R e se rved R e se rved R e se rved R e se rved R e se rved C o lo r S u b c a rrie r C on trol 1 C o lo r S u b c a rrie r C on trol 2 C o lo r S u b c a rrie r C on trol 3 C o lo r S u b c a rrie r C on trol 4 P ixel D ela y C o n tr o l M a n u a l C lo c k C o n trol 1 M a n u a l C lo c k C o n trol 2 M a n u a l C lo c k C o n trol 3 A u to C lo ck C o n trol A G C M o d e C o n tro l C hrom a G a in C o n tro l 1 C hrom a G a in C o n tro l 2 L u m a G a in C o n tro l 1 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 44 45 F1 F2 A D V A N C E D B LO C K R e se rved A n a lo g C o n trol (in te rn a l) A n a lo g C la m p C o n tro l D igita l C la m p C o n tr o l 1 D igita l C la m p C o n tr o l 2 S ha p i n g F ilte r C o n tro l R e se rved C o m b F ilte r C o n tro l R e se rved R e se rved R e se rved L u m a G a in C o n tro l 2 12 13 14 15 16 17 18 19 1A 1B 1C M a n u a l G a in S ha d o w C o n tro l 1 M a n u a l G a in S ha d o w C o n tro l 2 M isc G a in C o n tro l H syn c P o sitio n C o n tro l 1 H syn c P o sitio n C o n tro l 2 H syn c P o sitio n C o n tro l 3 P o la r ity C o n tr o l R e se rved R e se rved R e se rved R e se rved Figure 37. Subaddress Register 27 Rev. PrF 09/01 Rev. PrF 09/01 ADV7183 Table 1.0 Basic Registers R egister Nam e VID SEL.3 VID SEL.2 VID SEL.1 BETACAM OF SEL.3 GP EH GPEL FFM.4 CON.4 SAT.4 BRI.4 HUE.4 DEF Y.2 DEF C.4 TDR.1 PS CG STATUS.4 IDENT.4 BRI.3 HUE.3 DEF Y.1 DEF C.3 TDR.0 PS REF STATUS.3 IDENT.3 SAT.3 CON.3 FFM.3 FFM.2 CON.2 SAT .2 BRI.2 HUE.2 DEF Y.0 DEF C.2 TDC.1 PDBP STATUS.2 IDENT.2 GP0.3 GP0.2 FR CON.5 SAT.5 BRI.5 HUE.5 DEF Y.3 DEF C.5 TDR.2 PW RDN STATUS.5 IDENT.5 OF SEL.2 OF SEL.1 OF SEL.O COR.1 COR.0 YPM.2 YPM.1 OM SEL.1 GP0.1 FFM.1 CON.1 SAT .1 BRI.1 HUE.1 DEF_AUTO_EN DEF C.1 TDC.0 PSC.1 STATUS.1 IDENT.1 4FSC DIFFIN SQPE VID QUAL.1 TOD BL_C_VBI AFR CON.6 SAT .6 BRI.6 HUE.6 DEF Y.4 DEF C.6 TDR.3 TRAQ STATUS.6 IDENT.6 ASE VBI EN BT656-4 HL_EN FFST CON.7 SAT .7 BRI.7 HUE.7 DEF Y.5 DEF C.7 RES STATUS.7 IDENT.7 VID SEL.0 INSEL.3 INSEL.2 INSEL.1 addr (H ex) D7 D6 D4 D5 D3 D2 D1 D0 INSEL.0 VID QUAL.0 YPM.0 OMEL.O RANGE GP0.0 FFM.0 CON.0 SAT .0 BRI.0 HUE.0 DEF_VAL_EN DEF C.0 TDE PSC.0 STATUS.0 IDENT.0 Input C ontrol 00 Video Selection 01 Video Enha ncement C ontrol 02 O utput C ontrol 03 Extended O utput Control 04 G eneral P ur pose O utput 05 Reserved 06 F IF O Control 07 PRELIMINARY TECHNICAL DATA 28 Contrast C ontrol 08 Saturation C ontrol 09 B rightness Control 0A H ue C ontr ol 0B Default V alue Y 0C Default V alue C 0D Temporal D ec ima tion 0E P ower M anagement 0F Status Register 10 Info Register 11 Table 2.0 Advanced Registers R egister N am e D6 D5 D4 D1 TIM_OE FICL.1 DCC0 .9 DCC0.1 YSFM.1 YSFM.2 CCM .0 CSM F.26 CSM F.27 CSM F.19 CSM F.11 CSM F.3 CSM F.18 CSM F.10 CSM F.2 CSM F.25 CSM F.17 CSM F.9 CSM F.1 CCLEN DCFE DCC0 .4 YSFM.4 CCM B_AD CSM CSM F.20 CSM F.12 CSM F.4 CCM .1 YSFM.3 DCC0.3 DCC0.2 DCC0.11 DCC0.10 FACL.1 FACL.0 - ad dr (H ex) D7 D3 D2 DCCM DCT.1 DCC0.6 CSFM.1 CSM F.21 CSM F.13 CSM F.5 CSFM.0 DCC0.5 DCC0.7 CSFM.2 CSM F.23 CSM F.15 CSM F.7 CSM F.6 CSM F.14 CSM F.22 DCT.0 VCLEN - D0 FICL.0 DCC0.8 DCC0.0 YSFM.0 CSM F.24 CSM F.16 CSM F.8 CSM F.0 Reserved 12 Reserved 13 Analog Clamp Control 14 Digital Clamp Control 1 15 Digital Clamp Control 2 16 Shaping Filter Control 17 Reserved 18 PRELIMINARY TECHNICAL DATA 29 - Comb Filter Control 19 Color Subcarrier Control 1 23 Color Subcarrier Control 2 24 Color Subcarrier Control 3 25 Color Subcarrier Control 4 26 ADV7183 Rev. PrF 09/01 Rev. PrF 09/01 ADV7183 Table 2.1 Advanced Registers Continued R egister N am e D7 D6 CTA.2 CTA.0 CLKVAL.10 CLK VAL.2 CMG.10 CMG .2 LM G.10 LM G.2 LM GS.10 LM GS.2 LM GS.3 M IRE.1 HSB .3 HSE.3 HSE.4 PLLCR PF M IRE.0 HSB .2 HSE.2 PD V CLK VAL.9 CLK VAL.1 CLKVAL.17 CLKVAL.11 CLK VAL.3 CMG.11 CMG.3 LM G.11 LM G.3 LM GS.11 CLKVA5L.13 CLKVA5L.13 ACK LM .0 LAGC.0 CMG .4 LM G.4 LM GS.4 M IRE.2 HSE.8 HSB .4 LAGC.1 CMG .5 LM G.5 LM GS.5 HSE.9 HSB .5 HSE.5 P VS CLKVAL.4 CLKVAL.12 CTA.1 CLKM AN E CLKVAL.14 CLK VAL.6 ACK LM .1 LAGC.2 CAGT.0 CMG .6 LAGT.0 LM G.6 LM GS.6 CK E HSB .8 HSB .6 HSE.6 PHVR FSC _INV - ad dr (H ex) D5 D4 D3 D1 D2 D0 SW PC FIX27E CLKVAL.15 CLK VAL.7 ACKLM .2 CAGT.1 CMG .7 LAGT.1 LM G.7 SG UE LM GS.7 HSB .9 HSB .7 HSE.7 PHS - Pixel Delay Control 27 M anual Clock Control 1 28 CLKVAL.16 CLK VAL.8 CLK VAL.0 M anual Clock Control 2 29 M anual Clock Control 3 2A Auto Clock Control 2B CAGC.1 CMG .9 CMG .1 LM G.9 LM G.1 LM GS.9 LM GS.1 AV_AL HSB .1 HSE.1 PFF - CAGC.0 CMG .8 CMG .0 LM G.8 LM G.0 LM GS.8 LM GS.10 PW _UPD HSB .0 HSE.0 PCLK - AGC M ode Control 2C Chroma Gain Control 1 2D Chroma Gain Control 2 2E Luma Gain Control 1 2F PRELIMINARY TECHNICAL DATA 30 Luma Gain Control 2 30 M anual Gain Shadow Control 1 31 M anual Gain Shadow Control 2 32 M isc Gain Control 33 Hsync Position Control 1 34 Hsync Position Control 2 35 Hsync Position Control 3 36 Polarity Control 37 Resample control 44 Reserved 45 Reserved F1h Reserved F2h PRELIMINARY TECHNICAL DATA Register 00 Subad Register dress 00hex Input Control Bit Description INSEL [3:0] The INSEL bits allow the user to select an input channel as well as the input format 0 0 0 0 0 0 0 0 1 1 1 VID_SEL [3:0] The VID_SEL bits allow the user to select the input video standard 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 CVBS in on AIN1 CVBS in on AIN2 CVBS in on AIN3 CVBS in on AIN4 CVBS in on AIN5 CVBS in on AIN6 Y on AIN1, C on AIN4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Setting ADV7183 Composite S-Video Y on AIN2, C on AIN5 Y on AIN3, C on AIN6 Y on AIN1, U on AIN4, V on AIN5 Y on AIN2, U on AIN3, V on AIN6 YUV Auto detect PAL (BGHID), NTSC (without pedestal) Auto detect PAL (BGHID), NTSC (m) (with pedestal) Auto detect PAL (N), NTSC (M) (without pedestal) Auto detect PAL (N), NTSC (M) (with pedestal) NTSC (M) without pedestal NTSC (M) with pedestal NTSC 4.43 without pedestal NTSC 4.43 with pedestal PAL BGHID without pedestal PAL N with pedestal PAL M without pedestal PAL M with pedestal PAL combination N PAL combination N with pedestal : 31 Rev. PrF 09/01 ADV7183 Subad Register dress 01hex Video selection PRELIMINARY TECHNICAL DATA Bit Description VID_QUAL [1:0] allows the user to influence the time constant of the system depending on the input video quality. 0 0 1 1 SQPE Allows the use to enable/disable the square pixel operation. 0 1 DIFFIN Allows the user to select a differential input mode for every entry in the INSEL [3:0] table. 0 1 FFSC Four Fsc Mode This bit allows the selection of a special NTSC mode where the data is resampled to 4Fsc sampling rate. As a result the LLC will operate at a 4 Fsc rate as well. 0 1 BETACAM 0 1 RESERVED 0 ASE Automatic Startup Enable When set a change in the INSEL register will automatically be detected and lead the device to enter a video reacquire mode. May be disabled for genlocked video sources. 1 0 INSEL change will not cause reacquire INSEL change will trigger reacquire A zero must be written to this bit Standard video input Betacam input enable Standard Video operation Select 4 Fsc mode ( for NTSC only) Single ended inputs Differential inputs Only Valid for NTSC input. Standard mode Enable square pixel mode 0 1 0 1 Broadcast quality TV quality VCR quality Surveillance quality Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Setting Subad Register dress 02hex Video Enhancement Control Bit Description YPM [2:0] Y Peaking Filter Mode ,This function allows the user to boost/attenuate luma signals around the colour subcarrier frequency. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Setting Used to enhance the picture and improve the contrast 0 0 0 0 1 1 1 1 COR[1:0] Coring Selection, Controls optional coring of the Y output signal depending on its level. 0 0 1 1 Reserved 0 0 0 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 C=+4.5dB, S=+9.25dB C=+4.5dB, S=+9.25dB C=+4.5dB, S=+5.75dB C=+1.25dB, S=+3.3dB No Change C=+0,S=+0 C=-1.25dB, S=-3dB C=-1.75dB, S=-8dB C=-3.0dB, S=-8dB C=Composite(2.6Mhz ) S=S-Video (3.75Mhz) No Coring Truncate if Y 32 PRELIMINARY TECHNICAL DATA Subad Register dress 03hex Output Control Bit Description OM_SEL [1:0] Output Mode Selection. Selects the output mode as in the timing and interface type. 0 0 1 1 OF_SEL [3:0] Allows the user to choose from a set of output formats. 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TOD Tri-State Output Drivers. This bit allows the user to tri-state the output Drivers regardless of the state of the /OE pin. 0 1 VBI_EN Allows VBI data (lines 1 to 21) to be passed through with only a minimum amount of filtering performed. 0 1 All lines filtered and scaled Only active video region Drivers dependant on /OE pin Drivers tri-stated. 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reserved Reserved 16-bit@LLC2 4:2:2 CCIR656 8-bit@LLC 4:2:2 CCIR656 12-bit@LLC2 4:1:1 10-bit@LLC 4:2:2 CCIR656 8-bit@LLC 4:2:2 CCIR656 Reserved Reserved 8-bit@LLC 4:2:2 CCIR656 8-bit@LLC 4:2:2 CCIR656 Not Used Not Used Not Used Not Used Not Used 0 1 0 1 Philips compatible Broktree API A compatible Broktree API B compatible Not Valid setting Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Setting ADV7183 10-bit composite in 10-bit composite in with Debug signals I with Debug signals II Regardless of /OE pin Subad Register dress 04hex Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Setting Extended output RANGE Allows the user to select the control range of output values. Can be CCIR601 compliant or fill the whole accessible number range. 0 1 Reserved Bits DDOS [2:0] D Data Output selection. If the 100 pin package is used the 12 additional pins can output additional data. 0 BT656-4 Allows the user to select an output mode that is compatible with BT656-4 or BT656-3. 0 1 BT656-3 compatible BT656-4 compatible 0 0 No additional data 12 pins tri-state 1 1 0 CCIR compliant Fill whole accessible range 33 Rev. PrF 09/01 ADV7183 Subad Register dress 05hex PRELIMINARY TECHNICAL DATA Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Setting Pixel Data Valid off General purpose GPO [3:0] These general purpose Output outputs pins may be programmed by the user but are only available in selected output modes OF_SEL[3:0] and when the output drivers are enabled using GPEL ,GPEH and HL_Enable bits. 0 GPEL General Purpose enable low This bit enables the output drivers for the general purpose outputs bits 0 and 1. 0 1 GPEH General Purpose enable low This bit enables the output drivers for the general purpose outputs bits 3 and 2. 0 1 BL_C_VBI Blank Chroma during VBI 0 1 HL_EN Hlock Enable This bit causes the General Purpose output [0] pin to output Hlock instead of GPO [0]. Only available in certain output modes. 0 1 0 0 0 User Programmable HD Test pattern off GPO[1:0] tri-stated GPO[1:0] enabled GPO[3:2] tri-stated GPO[3:2] enabled Decode and output colour during VBI Blank Cr and Cb data during VBI Disabled General Purpose output (lwr bits) must be enabled GPEL GPO[0] pin function GPO[0] shows Hlock status Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Setting Suba Register ddres s 07h Fifo Control Bit Description FFM [4:0] Fifo flag margin The FFM register allows the user to program the location at which the FIFO flag's AEF and AFF. 0 FR Fifo reset Setting this bit will cause the FIFO to reset. 0 1 AFR Automatic Fifo reset Setting this bit will cause the FIFO to automatically reset at the end of each field of video 0 1 FFST Fifo Flag Self Time Set weather the Fifo flags AEF,AFF and HFF are output synchronous to the external CLKIN of the 27Mhz internal clock. 0 1 Synchronous to CLKIN Synchronous to 27Mhz No auto reset Auto reset Normal operation FIFO reset bit is auto cleared 0 1 0 0 User programmable 08h Contrast register CON[7:0] Contrast Adjust This is the user control for contrast adjustment 1 0 0 0 0 0 0 0 Rev. PrF 09/01 34 PRELIMINARY TECHNICAL DATA ADV7183 Suba Register ddres s 09h Saturation register Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Setting SAT[7:0] Saturation Adjust This allows the user to adjust the saturation of colour output 1 0 0 0 0 0 0 0 BRI[7:0] This register controls the brightness of the video signal. 0 0 0 0 0 0 0 0 The resolution is 1bit=.7 0 0 0 0 0 0 0 0 Range -90 with h00= 0 HUE[7:0] This register contains the value for the colour hue adjustment. 0Ah Brightness register 0Bh Hue Register 0Ch Default Value Y DEF_ VAL_ EN Default Value Enable 0 1 DEF_ VAL_ AUTO_EN Default Value Auto Enable In the case of lost lock enables/disables default values. 0 1 DEF_Y[5:0] Default Value Y This register hold the Y default value 0 0 0 1 0 0 Cr[7:0]={DEF_C[7:4 ],0,0,0,0} 1 0 0 0 1 0 0 0 Cb[7:0]={DEF_C[ 3:0],0,0,0,0} Use programmed value Use default value When lock is lost Use programmed value Use default value Y, Cr and Cb values 0Dh Default Value C DEF_C[7:0] Default Value C . Cr and Cb default values are defined in this register. 35 Rev. PrF 09/01 ADV7183 Suba Register ddres s 0Eh Temporal Decimation PRELIMINARY TECHNICAL DATA Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Setting TDE Temporal Decimation Enable bit allows the user to enable/disable the temporal function. 0 1 TDC[1:0] Temporal Decimation Control allows the user to select the suppression of selected fields of video. 0 0 1 1 TDR[3:0] Temporal Decimation Rate specifies how many fields/frames as to be skipped before a valid one is output 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Reserved 0 Set to Zero 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Skip no Field/Frame Skip 1 Field/Frame Skip 2 Fields/Frames Skip 3 Fields/Frames Skip 4 Fields/Frames Skip 5 Fields/Frames Skip 6 Fields/Frames Skip 7 Fields/Frames Skip 8 Fields/Frames Skip 9 Fields/Frames Skip 10 Fields/Frames Skip 11 Fields/Frames Skip 12 Fields/Frames Skip 13 Fields/Frames Skip 14 Fields/Frames Skip 15 Fields/Frames 0 1 0 1 Suppress frames, start with even field. Suppress frames, start with odd field. Suppress even fields only. Suppress odd fields only. Disabled Enabled Configured using TDC[1:0] and TDR[3:0] AS specified in the TDC[1:0] register Rev. PrF 09/01 36 PRELIMINARY TECHNICAL DATA Suba Register ddres s 0Fh Power Management Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Setting ADV7183 PSC[1:0] Power Save Control allows the a set of different power save modes to be selected . 0 0 1 1 PDBP Power Down Bit Priority There are two ways to shut down the digital core, the Power Down Bit which has higher priority 0 1 PS_REF Power Save Reference allows the user to enable/disable the internal analog reference. 0 1 PS_CG Power Save For the LLC Clock Generator 0 1 PWRDN Power Down Disables the input pads and powers down the 27Mhz clock 0 1 TRAQ Timing ReAquire will cause the part to reaquire the video signal and is the software version of the ISO pin. 0 1 Reserved 0 Reserved Bit set to Zero Normal Operation Require Video signal System functional PowerDown If bit is set will clear its self on the next 27Mhz clk cycle Clock Generator functional CG in Power Save Mode Reference Functional Reference in Pwr. Save mode Pwr. Dwn. Controller by Pin Pwr. Dwn. Controller by Bit 0 1 0 1 Full Operation CVBS input only Digital only Power Save Mode 10h Status Register Read only Status[7:0] Provides information about the internal status of the decoder. x x x x x x x x 0=v85a , 3=v85b , 4=v85b3 11h Info Register Read Only IDENT[7:0] Provides identification on the revision of the part. x x x x x x x x 37 Rev. PrF 09/01 ADV7183 Suba Register ddres s 13h Analog Control Internal PRELIMINARY TECHNICAL DATA Bit Desciption Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Setting TIM_OE Timing Signals Output Enables the user to force the output drivers for H-SYNC,VSYNV and Field into an active state regardless of the OE pin and TOD bit. 0 1 Reserved 0 1 0 0 0 1 1 Set at Default Value Dependant on OE and TOD HS,VS,F forced active 14h Analog Clamp Control FICL[1:0] Fine Clamp Length controls the number of clock cycles for which the slow current is on. 0 0 1 1 FACL[1:0] Fast Clamp Length controls the number of clock cycles for which the fast current is on. 0 0 1 1 CCLEN Current Clamp Enable allows the user to switch off the I sources in the analog front end 0 1 VCLEN Voltage Clamp Enable bit allows the user to disable the voltage clamp circuitry 0 1 Reserved 0 0 Reserved set to Zero Voltage Clamp disabled Voltage Clamp enabled I sources switched off I sources enabled 0 1 0 1 I on for 16 clock cycles I on for 32 clock cycles I on for 64 clock cycles I on for 128 clock cycles 0 1 0 1 I on for 16 clock cycles I on for 32 clock cycles I on for 64 clock cycles I on for 128 clock cycles Rev. PrF 09/01 38 PRELIMINARY TECHNICAL DATA ADV7183 Note Suba Register ddres s 15h Digital Clamp Control 1 Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comment DCCO[11:8] Digital Colour Clamp Offset holds upper 4-bits of the digital offset value which gets added to the raw data from the ADC before entering the core. x DCFE Digital Clamp Freeze Enable allows the user to freeze the digital clamp loop at any point in time 0 1 DCT [1:0] Digital Clamp Timing determines the time constant of the digital clamping circuitry 0 0 1 1 DCCM[7:0] Digital Colour Clamp Mode sets the mode of operation for the digital clamp circuitry 0 1 0 1 0 1 x x x Only applicable if DCCM is set to manual offset mode Digital clamp operational Digital clamp frozen Slow (TC: 1 sec) Medium (TC: 0.5 sec) Fast (TC: 0.1 sec) Dependent on VID_QUAL Offset correction via DCCO for C only Automatic digital clamp Manual Offset correction Only applicable if DCCM is set to manual offset mode 16h Digital Clamp Control 2 DCCO[7:0] Digital Colour Clamp Offset holds the lower 8bits of the digital offset value which gets added to the raw data from the ADC before entering the core. x x x x x x x x 39 Rev. PrF 09/01 ADV7183 Suba Register ddres s 17h Shaping Filter Control PRELIMINARY TECHNICAL DATA Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comment Note YSFM[4:0] Y Shaping Filter Mode allows the user to select a wide range of low pass and notch filters. 0 0 0 ~ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CSFM[2:0] C Shaping Filter Mode allows the selection from a range of low pass chrominance filters. 0 0 0 ~ 1 1 0 0 1 ~ 1 1 0 1 0 ~ 0 1 Auto selection 1.5Mhz Auto selection 2.17Mhz SH1 ~ SH5 SH6 0 0 0 ~ 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 ~ 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 ~ 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 ~ 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Auto Wide notch Auto Narrow notch SVHS 1 ~ SVHS 17 PAL NN1 PAL NN2 PAL NN3 PAL WN 1 PAL WN 2 NTSC NN1 NTSC NN2 NTSC NN3 NTSC WN1 NTSC WN2 NTSC WN3 Not Used SVHS 18 Auto = filter selected based on scaling factor. Rev. PrF 09/01 40 PRELIMINARY TECHNICAL DATA ADV7183 Note Suba Register ddres s 19h Comb Filter Control Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comment Reserved 0 CCM[1:0] Chroma Comb Mode selects a primary mode for the filter 0 0 1 1 CCMB_AD Chroma Comb Adaptive 0 1 Reserved 0 0 0 Set to Zero Chroma Comb nonadaptive Chroma Comb adaptive 0 1 0 1 No Comb 1H 2H Not Valid, do not use 0 Set to Zero 23h Colour Subcarrier Control 1 CSMF[27:24] Colour Subcarrier Manual Frequency Holds the value used to enable the user support odd subcarrier frequencies x CSM Colour Subcarrier Manual 0 1 Reserved 1 1 1 Set to One Manual Fsc. Disabeled User defined Fsc. Defined in CSFM[27:0] x x x 24h Colour Subcarrier Control 2 CSMF[23:16] Colour Subcarrier Manual Frequency Holds the value used to enable the user support odd subcarrier frequencies x x x x x x x x CSMF[15:8] Colour Subcarrier Manual Frequency Holds the value used to enable the user support odd subcarrier frequencies x x x x x x x x CSMF[7:0] Colour Subcarrier Manual Frequency Holds the value used to enable the user support odd subcarrier frequencies x x x x x x x x 25h Colour Subcarrier Control 3 26h Colour Subcarrier Control 4 41 Rev. PrF 09/01 ADV7183 Suba Register ddres s 27h Pixel Delay Control PRELIMINARY TECHNICAL DATA Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comment Note Reserved 0 CTA[2:0] Chroma Timing Adjust allows a specified timing difference between the Luma and Chroma samples 0 0 0 0 1 1 1 1 Reserved 1 SWPC This bit allows the Cr and Cb samples to be swapped. 0 1 No swapping Swap the Cr and Cb values Set to One 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Not valid setting Chroma+2 pixel (early) Chroma+1 pixel (early) No Delay Chroma-1 pixel (late) Chroma-2 pixel (late) Chroma-3 pixel (late) Not valid setting 0 0 Set to Zero 28h Manual Clock Control 1 CLKVAL[17:16] If enabled via CLKMANE then CLKVAL[17:0] determines the fixed output freq. On the LLC,LLC2 and LLCRef pins. x Reserved 1 CLKMANE Clock Generator Manual Enable allows the analog clock generator to produce a fixed clock frequency which is not dependent on the video signal 0 1 FIX27E Allows the o/p of fixed 27Mhz crystal clock via LLC,LLC2 and LLCRef o/p pins. 0 1 O/p freq set by clock gen. O/p 27Mhz fixed. O/p freq set by video freq set by CLKVAL[17:0] 1 1 1 Set to Default x 29h Manual Clock Control 2 Manual Clock Control 3 CLKVAL[15:8] See above x x x x x x x x 2Ah CLKVAL[7:0] See above x x x x x x x x Rev. PrF 09/01 42 PRELIMINARY TECHNICAL DATA ADV7183 Note Suba Register ddres s 2Bh Auto Clock Control Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comment Reserved 0 ACLKN[2:0] Automatic Clock Generator Mode influences the mode of operation for the LLC 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 Set to Zero Only when NOT in manual mode Colour Burst line Start:line24 colour burst line Active Video Active Video(<304) PAL Active Video(<304) PAL ActiveVideo(<319/320) PAL Invalid Invalid (<264)NTSC (<256)NTSC (<273/274)NTSC 2Ch AGC Mode Control CAGC[1:0] Chroma Automatic Gain Control selects the basic mode of operation for the AGC in the chroma path. 0 0 1 1 Reserved 1 LAGC[2:0] Luma Automatic Gain Control selects the mode of operation for the gain control in the luma path 0 0 0 0 0 1 1 0 1 0 1 Manual Fixed gain Use luma gain for chroma Automatic gain Freeze chroma gain Set to One Use CMG[11:0] Based on colour burst Manual Fixed gain AGC no override through white peak. Man IRE control AGC auto override through white peak. Man IRE control AGC no override through white peak. Auto IRE control AGC auto override through white peak. Auto IRE control AGC active video with white peak AGC active video with average video. Freeze gain Set to One Use LMG[11:0] Blank level to sync tip Blank level to sync tip Blank level to sync tip Blank level to sync tip 0 1 0 0 1 1 1 0 0 1 1 1 Reserved 1 0 1 1 1 0 1 43 Rev. PrF 09/01 ADV7183 PRELIMINARY TECHNICAL DATA Suba Register ddres s 2Dh Chroma Gain Control 1 Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comment Note CMG[11:8] Chroma Manual Gain can be used program a desired manual chroma gain or read back the actual used gain value x Reserved 1 CAGT[1:0] Chroma Automatic Gain Timing allows adjustment of the Chroma AGC tracking speed 0 0 1 1 0 1 0 1 1 x x x CAGC[1:0] settings will decide what mode CMG[11:0] operates in Set to One Will only have effect if CAGC[1:0] is set to auto gain (10) Slow (TC: 2 sec) Medium (TC: 1 sec) Fast (TC: 0.2 sec) Dependent on VID_QUAL 2Eh Chroma Gain Control 2 CMG[7:0] Chroma Manual Gain lower 8-bits ,see CMG[11:8] for description x 2Fh Luma Gain Control 1 LMG[11:8] Luma Manual Gain can be used program a desired manual chroma gain or read back the actual used gain value x x x x x x x LAGC[1:0] settings will decide what mode LMG[11:0] operates in x Reserved 1 LAGT[1:0]Luma Automatic Gain Timing allows adjustment of the Luma AGC tracking speed 0 0 1 1 30h Luma Gain Control 2 LMG[7:0] Luma Manual Gain can be used program a desired manual chroma gain or read back the actual used gain value x Suba Register ddres s 31h Manual Gain Shadow Control 1 Bit Description x x x x 0 1 0 1 1 x x x Set to One Will only have effect if LAGC[1:0] is set to auto gain (001,010,011or 100) Slow (TC: 2 sec) Medium (TC: 1 sec) Fast (TC: 0.2 sec) Dependent on VID_QUAL LAGC[1:0] settings will decide what mode LMG[11:0] operates in x x x Note Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comment LMGS[11:8] Luma Manual Gain Store has dual functions, a desired manual luma gain can be programmed or a readback from the register will return the actual gain used. x Reserved 1 SGUE Surveillance Gain Update Enable enables surveillance mode operation see LMGS[11:0] for details 0 1 1 1 x x x The function and readback value are dependant on LAGC[2:0] setting. Gain value will only become active when LAGC[2:0] set to manual fixed gain. Set to One Disable LMGS update Use LMGS update facility 32h Manual Gain Shadow Control 2 LMG[7:0] Chroma Manual Gain lower 8-bits ,see LMG[11:8] for description x x x x x x x x Rev. PrF 09/01 44 PRELIMINARY TECHNICAL DATA Suba Register ddres s 33h Misc Gain Control Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comment ADV7183 Note PW_UPD Peak White Update determines the gain based on measurements taken from the active video, this bit determines the rate of gain change. 0 1 AV_AL Average Brightness Active Lines Allows the selection between two ranges of active video to determine the average brightness 0 1 Mire[2:0] Max IRE Sets the max. I/p IRE level dependent on the video standard 0 0 0 0 1 1 1 1 Reserved 1 CKE Colour Kill Enable allows the optional colour kill function to be switched on or off. 0 1 Reserved 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LAGC[1:0] Must be set to the appropriate mode to enable peak white or average video in the first case Update gain once per line Update gain once per field Lines 33-310 Lines 33-270 PAL-133 NTSC-122 PAL-125 NTSC-115 PAL-120 NTSC-110 PAL-115 NTSC-105 PAL-110 NTSC-100 PAL-105 NTSC-100 PAL-100 NTSC-100 PAL-100 NTSC-100 Set to one Colour Kill disabled Colour Kill enabled Set to one Suba Register ddres s 34h Hsync Position Control 1 Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comment Note Reserved 1 HSE[9:8] HSync End allows the positioning of the HSync output within the video line 0 HSB[9:8] HSync begin allows the positioning of HSync output within the video line 0 0 0 HSync starts after HSB[9:0] pixel after the falling edge of HSync 1 1 1 Set to One HSync ends after HSE[9:0] pixel after falling edge of HSync 35h Hsync Position Control 2 HSB[7:0] See above, using HSB[9:0] and HSE[9:0] the user can program the position and length of HSync output signal 0 0 0 0 0 0 0 1 HSE[7:0] See above. 0 0 0 0 0 0 0 0 36h Hsync Position Control 3 45 Rev. PrF 09/01 ADV7183 Suba Register ddres s 37h Polarity PRELIMINARY TECHNICAL DATA Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comment Note PCLK Sets the polarity of LLC,LLC2 and QClk 0 1 PFF Sets the polarity of HFF,AEF and AFF 0 1 PDV Sets the polarity for Data Field 0 1 PF sets the field sync polarity 0 1 PLLCR sets the LLC Ref Polarity 0 1 PVS sets the Vsync Polarity 0 1 PHVR sets the Href and Vref sync polarities 0 1 PHS sets Hsync Polarity 0 1 Active High Active Low Note Active High Active Low Active High Active Low Active High Active Low Active High Active Low Active High Active Low Active High Active Low Active High Active Low Suba Register ddres s 44h Resample Control Bit Description Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comment Reserved Set to Default 0 FSC_INV Colour Subcarrier RTCO Inversion allows the inversion of the GL bit x 0 1 Reserved 0 Set to zero 0 0 1 1 x 1 x 1 0 0 1 1 1 1 Default Value Set to these values NB No Default Value Compatible ADV7190/91/94 Compatible with ADV717x Reserved Reserved Functions 0 1 F1h Reserved Reserved Functions 1 1 1 1 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 x 1 x 0 Default values Set to these values Default values Set to these values F2h Reserved Reserved Functions 1 1 Rev. PrF 09/01 46 PRELIMINARY TECHNICAL DATA POWER ON RESET VALUES R egister N a m e B A S IC B LO C K In pu t C on trol V ideo S election V ideo E n hanc em en t C ontro l O ut p ut C on tro l E xte n ded O ut p ut C on trol G ene ral P urp ose O utp ut Reserved FIF O C o n tr ol C ontras t C on tr ol S atu rati on C ontrol B ri ghtn ess C on trol H ue C o n tr ol D efault V alue Y D efault V alue C T em pora l D eci m ation P ower M an agem en t S tatus Regis ter In fo Regis ter ADV7183 addr (H ex) D efa u lt (H ex) addr (H ex) D efa u lt (H ex) R egister N a m e A D V A N C E D B LO C K 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 00 80 04 0C 0C 40 04 80 80 0 0 10 88 00 00 - R e se rve d R e se rve d R e se rve d R e se rve d R e se rve d R e se rve d C o lo r S u b c a r rie r C o n tr o l 1 C o lo r S u b c a r rie r C o n tr o l 2 C o lo r S u b c a r rie r C o n tr o l 3 C o lo r S u b c a r rie r C o n tr o l 4 P ixe l D e la y C o n tr o l M a n u a l C lo c k C o n tr o l 1 M a n u a l C lo c k C o n tr o l 2 M a n u a l C lo c k C o n tr o l 3 A u to C lo c k C o n tr o l A G C M o d e C o n tro l C hr o m a G a in C o n tr o l 1 C hr o m a G a in C o n tr o l 2 L u m a G a in C o n tr o l 1 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 44 45 F1 F2 xx xx xx xx xx xx Ex xx xx xx 58 xx xx xx A0 CE Fx xx Fx xx 7x xx E3 0F 01 00 00 x1 xx Fx 9x A D V A N C E D B LO C K R e se rve d A n a lo g C o n tr o l (in te rn a l) A n a lo g C la m p C o n tr o l D ig ita l C la m p C o n tr o l 1 D ig ita l C la m p C o n tr o l 2 S ha p in g F ilte r C o n tro l R e se rve d C o m b F ilt e r C o n tr o l R e se rve d R e se rve d R e se rve d L u m a G a in C o n tr o l 2 12 13 14 15 16 17 18 19 1A 1B 1C 45 18 6x xx 01 10 xx xx xx M a n u a l G a in S ha d o w C o n tro l 1 M a n u a l G a in S ha d o w C o n tro l 2 M isc G a in C o n tro l H syn c P o sitio n C o n t ro l 1 H syn c P o sitio n C o n t ro l 2 H syn c P o sitio n C o n t ro l 3 P o la r ity C o n tr o l R e se rve d R e se rve d R e se rve d R e se rve d 47 Rev. PrF 09/01 ADV7183 PRELIMINARY TECHNICAL DATA APPENDIX 1 BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7183 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system level design such that high speed, accurate performance is achieved. The Recommended Analog Circuit Layout shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV71785 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of VDD and GND pins should by minimized so as to minimize inductive ringing. Ground Planes Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode. Supply Decoupling For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 F ceramic capacitor decoupling. Each group of VDD pins on the ADV71785 must have at least one 0.1 F decoupling capacitor to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV7183 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three terminal voltage regulator for supplying power to the analog power plane. Digital Signal Interconnect The ground plane should encompass all ADV7183 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7183, the analog output/input traces, and all the digital signal traces leading up to the ADV7183. The ground plane is the board's common ground plane. The ADV7183 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (VDD). This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7183. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7183 power pins and voltage reference circuitry. Power Planes The digital inputs to the ADV7183 should be isolated as much as possible from the analog inputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7183 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane. Analog Signal Interconnect The ADV7183 should be located as close as possible to the input connectors to minimize noise pickup and reflections due to impedance mismatch. The video input signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. Digital Outputs, especially Pixel Data Inputs and clocking signals should never overlay any of the analog signal circuitry and should be kept as far away as possible. The ADV7183 should have no inputs left floating. Any inputs that are not required should be tied to ground. Rev. PrF 09/01 48 PRELIMINARY TECHNICAL DATA ADV7183 AVSS DVSS AVDD F E R IT E B E A D 33 F 10 F AVSS 10 F AVSS 0. 1F AVSS 0.1 F DVSS 0. 01 F AVSS 0.0 1 F DVSS P O W E R S U P P LY D E C O U P LIN G FO R E ACH P O W E R PIN P O W E R S U P P LY D E C O U P LIN G FO R E ACH P O W E R PIN DVDD 33 F F E R IT E B E A D DVSS 10 0n F DVSS AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 10 0n F 10 0n F 100 n F 10 0n F 100 n F AIN1 AV S S 1 AIN2 AV S S 2 AIN3 AV S S 3 AIN4 AV S S 4 AIN5 AV S S 5 AIN6 AV S S 6 D V D D I O D V D D A V D D A D V 71 8 3 AVSS AVSS AVSS AVSS AVSS AVSS IN P U T S W IT C H OVER 0.1F 10 F 0.1F 0.1 F PO P1 P2 P3 P4 P5 P6 P7 P8 P9 P 10 P 11 P 12 P 13 P 14 P 15 GP O 0 GP O 1 GP O 2 GP O 3 LLC LLC 2 MULTI FORMAT P IX E L PO RT P 15 -P 8 8 -b it C C I R 6 56 P IX E L D A T A @ 2 7M H z P 7-P 0 C b & C r 1 6-bit C C IR 656 P IX E L D A T A @ 1 3.5M H z P 1 5-P 8 Y 1 & Y 2 1 6-bit C C IR 656 P IX E L D A T A @ 13 .5 M H z ISO CA P Y 1 CA P Y 2 27M H z O U T P U T C LO C K 13.5 M H z O U T P U T C LO C K C L O C K R E F E R E N C E O /P AVSS AVSS 0.1 F 10 F 0.1 F 0. 1F LLC R EF CA P C 1 CA P C 2 AE F AFF RD OE A LM O S T E M P T Y F IF O O /P A LM O S T F U L L F IF O O /P R E A D S IG N A L I/P O U T P U T E N A B L E I /P D A T A V A L ID O /P G L/Q C L K /H F F O / P F IF O M A N A G E M E N T S I G N A L S O N LY U S E D IN F IF O M O D E , U S E LL C A N D G E N LO C K F O R N O N F IF O M O D E AVSS AVSS CM L RE FO U T DV GL /QCL K/HF F 0.1F 10 F 0. 1F AVSS 33 pF DVDD 27 M H z DVSS 33p F DVSS DVSS XTA L PW R DN POW ER DOW N IN P U T XTA L1 HS /H R E S E T VS /V R E S E T FIELD H S / H R E S E T O /P V S /V R E S E T O /P F IE LD O /P DVDD DVDD A LS B 2K 2K 100R M PU INT ER FA CE C O N T R O L LIN E S DVDD SC LK 100R EL P F 5K6 68 p F 2nF SD A R ESE T 4K7 RESET 10 0 n F DVSS AVDD Figure 1. Recommended Circuit Layout 49 Rev. PrF 09/01 ADV7183 PRELIMINARY TECHNICAL DATA O U T L IN E D IM E N S IO N S D im e n s io n s s ho w n in in c h e s a n d (m m ). 8 0 -L e a d L Q F P (S T -8 0) 0.6 4 0 ( 16 .2 5) 0.6 2 0 ( 15 .7 5) 0.0 6 3 (1 .60 ) M AX 0.0 3 0 (0 .75 ) 0.0 2 0 (0 .50 ) 61 60 41 40 0.5 5 3 ( 14 .0 5) 0.5 4 9 ( 13 .9 5) 0. 48 6 (12 .35 ) TY P SE ATIN G PLAN E 0.4 86 (12 .35 ) T Y P 0.5 5 3 ( 14 .0 5) 0.6 4 0 ( 16 .2 5) 0.5 49 (1 3.9 5 0.6 2 0 ( 15 .7 5) TO P VI E W (P IN S D O W N ) 0. 00 4 (0.1 0) M AX 0.0 0 6 (0 .15 ) 0.0 0 2 (0 .05 ) 0.0 5 7 (1 .45 ) 0.0 5 3 (1 .35 ) 80 1 20 21 0.0 2 9 (0 .73 ) 0.0 2 2 (0 .57 ) 0.0 1 4 (0 .35 ) 0.0 1 0 (0 .25 ) Rev. PrF 09/01 50 |
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